keyboard circuit

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keyboard circuit

hello everyone
I have an external keyboard that is essentially a switch matrix, just like the Werkstatt keyboard, except it has 37 buttons instead of 13.
I'd like to build a circuit, like the Werkstatt keyboard circuit on sheet n.5, that would allow me to employ my 37-keys keyboard (with CV out off course).
I don't understand how I can replicate and expand the circuit on sheet n.5 to handle 37 buttons. I only managed to get 3 more buttons, that was easy (indeed the CD40175 has got 4 output so you can get 16 voltages at max on the TL072 input).
I'd like to note that I don't want to use a uC to control the keyboard, and that I can solder (smd parts too) and etch pcbs, so the only problem is understanding the circut :D

Byron J
So lets walk through the

So lets walk through the schematic for the key scanner, and look at what the various pieces do. It might help to follow along - I'll use the coordinates on the page to help navigate.

The circuit at D6 is a clock oscillator. It generates a square wave at roughly 150 kHz, known as "KB_CLK" on the page.

At C6 are a pair of 4 bit binary counters. The first one (U18A) is counting clock pulses, and the 3rd bit of the first counter is daisy-chained to the second one (U19B). The least-significant bit is not connected to anything. The overall result is a 4 bit count that increments on every fourth clock cycle.

This 4-bit count, let's call it "D-BUS", is used a couple of different ways.

U16 and U19 values aren't marked on the schem - they're CD4051 analog multiplexer/demultiplexers.

The lower 2 bits drive the column output selection to the keypad via U16. It forms a one-hot selection signal: amongst C0, C1, C2 and C3, only one line will be pulled high at a time.

The upper 2 bits drive the row input selection. The output of this mux will cycle between R0, R1, R2 and R3 as the conter progresses.

So effectively, using U18, U16 and U19, we select a row (the MSBs move slower than the LSBs), then sequentially activate each column. If no switches are closed, the column selection signal doesn't show up at any of the row inputs. The output of U19, pin 3, will stay low, and we'll move on to the next row.

When a column/row combination finds a switch that is closed, U19 pin3 will return some of the voltage to U14, gate F, a schmitt trigger/inverter. This is again used several places.

C63/R86/D6 form an active-low pulse called "MR" (meaning maybe "memory reset"). MR resets the 4-bit counter, so the scan restarts from 0b0000. Resetting the counter when it finds a closed switch is how it implements low-note priority. When it finds a switch, it simply stops looking for anything higher.

U14-D reinverts the row signal, which is the gate. C68/R90/D15 turn rising edges of the gate into short pulses, which are the trigger signal, which is buffered through U14-B & C.

U14-E re-inverts the row voltage, forming the D-BUS_CLK signal. D-BUS_CLK causes the current 4-bit count on D-BUS to be stored by U15, a 4-bit flip-flop. The flip-flop feeds the R2R resistor ladder, an implementation of a D-to-A converter. The R2R if buffered by U13-A, which feeds the portamento circuit, which is buffered again by U13-B.

Also notice that if no key is held, the flip-flop continues holding the last value it saw - the CV output will hold the last note played, so if you have long release times, the note persists long after the gate is gone.

(I'll admit there are a couple of things I haven't fully groked yet. Why does it discard the LSB of the counter? C61 and C64 appear to be used to slow down some pulses - perhaps so the in-between clocks can do something? I may need to try a SPICE simulation to learn a bit more)


So if you follow all of that, growing the keyboard is a matter of increasing the width of the data bus. 4 bits gives us 16 possible key positions, 5 bits would gives us 32, and 6 bits would give us 64.

So we need to grow the data bus to 6 bits. The circuit to do that is almost there:

At U18-A and B, we need to use one more bit from each, and move the daisy-chain output one bit up, making a 6-bit counter & data bus. Those new bits connect to the C inputs of U16 and U19. That then fully utilizes the 3:8 mux/demux action they provide. The keys hang in expanded columns and rows, making an 8 by 8 array.

You'll then need 2 more bits of flip-flop the latch the new D_BUS bits. You'll also need another couple rungs on the resistor ladder to convert them.

If you want to drive the VCO in place of the keyboard CV, there's also a need to rescale the keyboard CV. By default, it's 5V/16, or 312 mV per semitone. By adding 2 more bits, it becomes 5V/64, or 78 mV per semitone. VR10 may allow the range to get there, or R39 may need to be scaled back, more akin to R46. Alternatively, just use EXP VCO CV IN patchpoint.

that is an awesome help!

that is an awesome help! really thank you!
this is what I've done so far (highlighed in red the modifications)

I hope I understood well and did not make a complete mess :-D
I added 4 more rows and 4 more columns to the 2 multiplexers, then added another bit to each counter (and moved the daisy chain from the 3rd bit to the 4th of the first counter).
Then I added another 40175 chip, and I used only the first two inputs (D1 and D2).
I connected the new 40175 clock pin and the older 40175 clock pin togheter.
I added other resistors on the new 2 outputs to convert them to analog voltages.
But I think I need to rearrange Q0-Q5 outputs now, since the 3rd bit should be on U15-A D3, and its successive bits should be moved of 1 position, right?

update: it seems to work :-D

update: it seems to work :-D
I tried it in a simulator, and it detects 64 inputs.
I had to rearrange the DAC input/output as I suspected in the previous post.
The max voltage is however 4.90V and not 5V, so the steps are more like 0,077V spaced than 0,078V. I think it is not an issue (if I would, I can multiply that for something like 0.X using an opamp), but I was wondering why.

Also, if it is possible, I would really love to add two features:

1) legato mode (using a simple switch):
when in legato mode, if you press a key, gate and triggers goes ON, but if you press another key keeping the previous key pressed, they won't retrigger.
when legato is off, if you press a key and then another key without releasing the previous, then it retriggers the note (for the envelope).
I hope I explained well (sorry for my bad english)

2) low note priority / high note priority / last played note priority selectable using a switch

Byron J
Wow. you're moving quickly.

Wow. you're moving quickly. The modified schem looks pretty good.

Have you actually built up the circuit, or only done the simulation? What platform do you use for the simulation?

To answer your questions:

Yes, the data lines to the DAC need to get rearranged. The new bit from U18A needs to be inserted in the middle, and then the bits from U18B fall in above it.

The DAC will never actually put out the whole reference voltage. With 6 bits, it divides the reference voltage by 2^6, or 64. But the 64 values it gives you will be 0 through 63. So at the top, you get 5V *(63/64) = 4.921. I'm not sure of that's part of what you're seeing. Are you saying that your power supply is only providing 4.9v?

Analog voltages are often off from the ideal calculated values...component tolerances contribute. If the supply voltage is off, then everything that uses it might be off as well. I recently built a MIDI converter for my Werkstatt, and used a TL431 voltage reference to get the scaling dialed in.

As for your other modes, you're starting to get into microcontroller territory. The WS-01 circuit is pretty specific, and not very flexible.

I think the feature you're calling "legato mode" is more commonly called "envelope retriggering."Not that it couldn't be done, but it might double the complexity of the circuit!

The note priority is also intrinsic in the WS-01 circuit. The counter only counts up. There are other ICs (called "up/down counters") that allow you to select whether they're counting up or down, which would let you select high/low priority. The last note priority is harder still...

I've had a little insight into some of the timing stuff I wasn't sure of when I wrote that beofre - I'll follow up in a bit.

I only did the circuit on a

I only did the circuit on a simulator, specifically Proteus.
Yes I meant that the top value I got was 4.9V so it is normal as you explained, 5*(63/64). I will boost the output a little using an opamp, so I can reach 1V/oct too and I can use the keyboard with many other gear.

thank you really much, it is a great help.

Do you think I need to boost the circuit clock frequency to overcome the time needed to decode the new switches?

Now I will start to think about how I can manage to get retriggering and "last played note priority". First thing I will try is to put a 4516 (up-down binary counter) instead of 4520

Byron J
I've been trying to build a

I've been trying to build a simulation of this myself, so I can understand the timing more precisely. I've been hung up in that I can't find a LTSPICE model of a CD4051, so that's not going anywhere at this second.

As for the clock frequency, I'd see what you think of the responsiveness with the 150 kHz might not be able to tell the sifference - I think it'll still update in less than a millisecond.

I'd be a littler nervous about cranking it too much higher. If it gets too fast, those RC circuits that slow down some of the edges (around C61, C63, etc) will no longer work properly, and the D-BUS_CLK pulse won't be generated.